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1 features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) 20 mhz clock rate byte mode and 256-byte page mode for program operations sector architecture: ? two sectors with 32k bytes each (512k) ? four sectors with 32k bytes each (1m) ? 128 pages per sector product identi fication mode low-voltage operation ? 2.7 (v cc = 2.7v to 3.6v) sector write protection write protect (wp ) pin and write disable instructions for both hardware and software data protection self-timed program cycle (60 s/byte typical) self-timed sector erase cycl e (1 second/sector typical) single cycle reprogramming (erase and program) for status register high reliability ? endurance: 10,000 write cycles typical lead-free devices available 8-lead jedec soic and 8-lead sap packages description the at25f512/1024 provides 524,288/1,048,576 bits of serial reprogrammable flash memory organized as 65,536/131,072 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low-power and low-volt- age operation are essential. the at25f512/1024 is available in a space-saving 8-lead jedec soic and 8-lead sap packages. the at25f512/1024 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all write cyc les are complete ly self-timed. block write protection for top 1/4, top 1/2 or the entire memory array (1m) or entire memory array (512k) is enabled by programming the status register. separate write enable and write disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. rev. 1440p?seepr?6/04 spi serial memory 512k (65,536 x 8) 1m (131,072 x 8) at25f512 at25f1024 pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input 8-lead soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead sap bottom view 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd
2 at25f512/1024 1440p?seepr?6/04 block diagram absolute maximum ratings* operating temperature ........................................? 40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +3.6v maximum operating voltage ............................................ 3.6v dc output current........................................................ 5.0 ma 65,536 x 8 or 131,072 x 8
3 at25f512/1024 1440p?seepr?6/04 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +3.6v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v dc characteristics applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +2.7v to +3.6v, t ac = 0 c to +70 c, v cc = +2.7v to +3.6v (unless otherwise noted). symbol parameter test co ndition min typ max units v cc supply voltage 2.7 3.6 v i cc1 supply current v cc = 3.6v at 20 mhz, so = open read 10.0 15.0 ma i cc2 supply current v cc = 3.6v at 20 mhz, so = open write 15.0 30.0 ma i sb standby current v cc = 2.7v, cs = v cc 2.0 10.0 a i il input leakage v in = 0v to v cc -3.0 3.0 a i ol output leakage v in = 0v to v cc , t ac = 0 c to 70 c -3.0 3.0 a v il (1) input low voltage -0.6 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 2.7v v cc 3.6v i ol = 0.15 ma 0.2 v v oh output high voltage i oh = -100 a v cc - 0.2 v
4 at25f512/1024 1440p?seepr?6/04 notes: 1. the programming time for n bytes will be equal to n x t bpc . 2. this parameter is characterized at 3.0v, 25 c and is not 100% tested. 3. one write cycle consists of erasing a sector , followed by programming the same sector. ac characteristics applicable over recommended operating range from t ai = -40 c to +85 c, v cc = +2.7v to +3.6v c l = 1 ttl gate and 30 pf (unless otherwise noted). symbol parameter min typ max units f sck sck clock frequency 0 20 mhz t ri input rise time 20 ns t fi input fall time 20 ns t wh sck high time 20 ns t wl sck low time 20 ns t cs cs high time 25 ns t css cs setup time 25 ns t csh cs hold time 25 ns t su data in setup time 5 ns t h data in hold time 5 ns t hd hold setup time 15 ns t cd hold time 15 ns t v output valid 20 ns t ho output hold time 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec erase cycle time per sector 1.1 s t bpc byte program cycle time (1) 60 100 s t sr status register write cycle time 60 ms endurance (2) 10k write cycles (3)
5 at25f512/1024 1440p?seepr?6/04 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25f512/1024 always operates as a slave. transmitter/receiver: the at25f512/1024 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code t hat defines the operations to be performed. invalid op-code: if an invalid op-code is received , no data will be shifted into the at25f512/1024, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the at25f512/1024 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25f512/1024. when the device is sele cted and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the 25f512/1024 has a write lockout feature that can be activated by asserting the write protect pin (wp ). when the lockout feature is activated, locked-out sectors will be read only. the write protect pin will allow normal read/write operations when held high. when the wp is brought low and wpen bit is ?1?, all write operations to the status register are inhibited. wp going low while cs is still low will in terrupt a write to the status register. if the internal status register write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the at25f512/1024 in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ?1?.
6 at25f512/1024 1440p?seepr?6/04 spi serial interface master: microcontroller slave: at25f512/1024 data out (mosi) data in (miso) serial clock (spi ck) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs si so sck cs
7 at25f512/1024 1440p?seepr?6/04 functional description the at25f512/1024 is designed to interface directly with the synchronous serial periph- eral interface (spi) of the 6800 type series of microcontrollers. the at25f512/1024 utilizes an 8- bit instruction regist er. the list of inst ructions and their operation codes are contained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low transition. write is defined as program and/or erase in this specification. the following commands, program, sector erase, chip erase, and wrsr are write instructions for at25f512/1024. write enable (wren): the device will power up in the write disable state when v cc is applied. all write instructions must therefore be preceded by the wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the wrdi instruction disables all write commands. the wrdi instruction is independent of the sta- tus of the wp pin. read status register (rdsr): the rdsr instruction provides access to the sta- tus register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. during internal write cycles, all other commands will be ignored except the rdsr instruction. table 1. instruction set for the at25f512/1024 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array program 0000 x010 program data into memory array sector erase 0101 x010 erase one sector in memory array chip erase 0110 x010 erase a ll sectors in memory array rdid 0001 x101 read manufacturer and product id table 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy
8 at25f512/1024 1440p?seepr?6/04 read product id (rdid): the rdid instruction allows the user to read the manufac- turer and product id of the device. the first byte after the instruction will be the manufacturer code (1fh = atmel), followed by the device code. write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection for the at25f1024. the at25f1024 is divided into four sectors where the top quarter (1/4), top half (1/2), or all of the memory sectors can be protected (locked out) from write. the at 25f512 is divided into 2 sectors where all of the memory sectors can be protected (locked out) from write. any of the locked-out sec- tors will therefore be read only. the lock ed-out sector and t he corresponding status register control bits are shown in table 4. the three bits, bp0, bp1, and wpen, are nonv olatile cells that have the same proper- ties and functions as the regular memory cells (e.g., wren, t wc , rdsr). table 3. read status register bit definition bit definition bit 0 (rdy ) bit 0 = 0 (rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1 = 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bp0) see table 4. bit 3 (bp1) see table 4. bits 4-6 are 0s when device is not in an internal write cycle. bit 7 (wpen) see table 5. bits 0-7 are 1s during an internal write cycle. table 4. block write protect bits level status register bits at25f512 at25f1024 bp1 bp0 array addresses locked out locked-out sector(s) array addresses locked out locked-out sector(s) 000 none none none none 1(1/4) 0 1 018000 - 01ffff sector 4 2(1/2) 1 0 010000 - 01ffff sector 3, 4 3(all) 1 1 000000 - 00ffff all sectors (1 - 2) 000000 - 01ffff all sectors (1 - 4)
9 at25f512/1024 1440p?seepr?6/04 the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the wp pin is high or the wpen bit is ?0.? when the device is hard- ware write protected, writes to the status register, including the block protect bits and the wpen bit, and the locked-out sectors in the memory array are disabled. write is only allowed to sectors of the memory which are not locked out. the wrsr instruction is self-timed to automatically erase and program bp0, bp1, and wpen bits. in order to write the status register, the device must first be write enabled via the wren instruction. then, the instruction and data for the three bits are entered. during the internal write cycle, all instructions will be ignored exc ept rdsr instructions. the at25f512/1024 will automatically return to write disable st ate at the completion of the wrsr cycle. note: when the wpen bit is hardware write prot ected, it cannot be changed back to ?0?, as long as the wp pin is held low. read* (read): reading the at25f512/1024 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read instruction is transmitted via the si line followed by the byte address to be read (refer to table 6). upon completion, any data on the si line will be ignored. the data (d7-d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read instruction can be continued since t he byte address is aut omatically incremented and data will continue to be shifted out. for the at25f1024, when the highest address is reached, the address counter will roll over to the lowest address a llowing the entire memory to be read in one continuous read instruction. for the at25f512, the read command must be termi- nated when the highest address (00ffff) is reached. program (program): in order to program the at25f512/1024, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the program instruction can be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field loca- tion selected by the block write protection level. during an internal self-timed programming cycle, all commands will be ignored except the rdsr instruction. the program instruction requires the following sequence. after the cs line is pulled low to select the device, the program instru ction is transmitted via the si line followed by the byte address and the data (d7-d0) to be programmed (refer to table 6). pro- gramming will start after the cs pin is brought high. the low-to-high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. table 5. wpen operation wpen wp wen protectedblocks unpr otectedblocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
10 at25f512/1024 1440p?seepr?6/04 the ready/busy status of the device can be determined by initiating a rdsr instruc- tion. if bit 0 = 1, the program cycle is still in progress. if bit 0 = 0, the program cycle has ended. only the rdsr instruction is enabled during the program cycle. a single program instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. the starting byte could be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. if more than 256 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. the same byte cannot be reprogrammed without erasing the whole sector first. the at25f512/1024 will auto matically return to the write disable state at the com- pletion of the program cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-initiate the serial communication. note: 1. for the at25f512, a16 must be set to zero. if a16 of the at25f512 is set to one, read data out are unde termined and program, sector erase and chip erase may incur busy cycles. sector erase (sector erase): before a byte can be reprogrammed, the sector which contains the byte must be erased. in order to erase the at25f512/1024, two sep- arate instructions must be executed. first, the device must be write enabled via the wren instruction. then the sector erase instruction can be executed. the sector erase instruction erases every byte in the selected sector if the sector is not locked out. sector address is automatically determined if any address within the sec- tor is selected. the sector erase instru ction is internally controlled; it will automatically be timed to completion. during this time, all commands will be ignored, except rdsr instruction. t he at25f512/1024 will automatically return to the write dis- able state at the completion of the sector erase cycle. chip erase (chip erase): as an alternative to the sector erase, the chip erase instruction will erase every byte in all sectors that are not locked out. first, the device must be write enabled via the wren instruction. then th e chip erase instruc- tion can be executed. the chip erase instru ction is internally controlled; it will automatically be timed to completion. the ch ip erase cycle time typically is 3.5 sec- onds. during the internal eras e cycle, all instructions will be ignored except rdsr. the at25f512/1024 will au tomatically return to the write disable stat e at the completion of the chip erase cycle. table 6. address key address at25f512 at25f1024 a n a 15 - a 0 a 16 - a 0 zeros a 16 (1) - don?t care bits a 23 - a 17 a 23 - a 17 table 7. sector addresses sector address at25f512 sector at25f1024 sector 000000 to 007fff sector 1 sector 1 008000 to 00ffff sector 2 sector 2 010000 to 017fff n/a sector 3 018000 to 01ffff n/a sector 4
11 at25f512/1024 1440p?seepr?6/04 timing diagrams (for spi mode 0 (0, 0)) synchronous data timing wren timing wrdi timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
12 at25f512/1024 1440p?seepr?6/04 rdsr timing wrsr timing read timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance 15 cs si sck high impedance instruction 3-byte address 01234 4 5 5 6 6 7 7 8 9 10 11 28 23 22 21 3 ... 21 321 0 0 29 30 31 32 33 34 35 36 37 38 so 39
13 at25f512/1024 1440p?seepr?6/04 program timing hold timing sector erase timing cs sck si so 3-byte address 1st byte data-in 256th byte data-in instruction high impedance 0123456789101128 23 22 21 3 1 0 6 5 4 3 2 1 0 7 2 29 30 31 32 33 34 2075 2076 2078 2077 2079 so sck hold t cd t hd t hz t lz t cd t hd cs x x = don?t care bit
14 at25f512/1024 1440p?seepr?6/04 chip erase timing rdid timing x x = don?t care bit 12 13 14 15 16 17 23 18 19 x manufacturer code (atmel) device code
15 at25f512/1024 1440p?seepr?6/04 ordering information ordering code package operation range at25f512n-10si-2.7 8s1 industrial (-40 c to 85 c) at25f1024n-10si-2.7 8s1 industrial (-40 c to 85 c) at25f512n-10su-2.7 at25f512y4-10yu-2.7 8s1 8y4 lead-free/halogen free/industrial temperatures (-40 c to 85 c) at25f1024n-10su-2.7 at25f1024y4-10yu-2.7 8s1 8y4 lead-free/halogen free/industrial temperatures (-40 c to 85 c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8y4 8-lead, 6.00 mm x 4.90 mm body, dual footpr int, non-leaded, small array package (sap) options -2.7 low-voltage (2.7v to 3.6v)
16 at25f512/1024 1440p?seepr?6/04 package drawing 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at25f512/1024 1440p?seepr?6/04 8y4 ? sap 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0 8 17 title drawing no. r rev. 8 y4 , 8 -le a d (6.00 x 4.90 mm body) s oic arr a y p a ck a ge ( s ap) y4 a 8 y4 5/24/04 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 0.90 a1 0.00 ? 0.05 d 5. 8 0 6.00 6.20 e 4.70 4.90 5.10 d1 2. 8 5 3 .00 3 .15 e1 2. 8 5 3 .00 3 .15 b 0. 3 5 0.40 0.45 e 1.27 typ e1 3 . 8 1 ref l 0.50 0.60 0.70 a e a1 b pin 1 index area d a pin 1 id e1 d1 l e e1
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